1. Field
Example non-limiting embodiments relate to a semiconductor device and a method of fabricating the same, for example, to a semiconductor chip and a method of fabricating the same.
2. Description of the Related Art
In recent years, with the production of compact-sized semiconductor products, efforts have been continuously made to reduce the thickness of a semiconductor package. One of the methods of reducing the thickness of a semiconductor package is to perform a back-side polishing process on a semiconductor substrate. Through the back-side polishing process, unnecessary electric junction of a semiconductor substrate body interfering with back contact conduction may be removed, and the heat releasing performance of the semiconductor package may be improved.
For example, a thickness of the semiconductor substrate passing through the back-side polishing process may be reduced from about 850 μm to 50 μm. After the back-side polishing process, the semiconductor substrate may pass through a dicing process, and may be made into semiconductor chips. The resultant semiconductor chip may be connected to another semiconductor chip or a packaging die, for example, a lead frame or printed circuit board.
FIG. 1A is a schematic view of a conventional semiconductor substrate provided with an elastic protecting layer.
Referring to FIG. 1A, a semiconductor device pattern 20 may be formed on a semiconductor substrate 10. The semiconductor device pattern 20 may include a plurality of hetero-materials having different thermal expansion coefficients, for example, an insulating layer composed of oxide or nitride and a metal layer composed of tungsten (W) or aluminum (Al). A passivation layer 30 may be stacked to protect the semiconductor device pattern 20 on the semiconductor substrate.
The semiconductor device pattern 20 and the passivation layer 30 may be composed of materials that are easily breakable, and they may be damaged due to a contact with a package die (not shown) that may envelop them or an external impact. Generally, an elastic protecting layer 40 with sufficient mechanical intensity and elasticity may be provided on the passivation layer 30 in order to protect the semiconductor device pattern 20 and the passivation layer 30. For example, the elastic protecting layer 40 may provide thermal conductivity for heat releasing, thermal resistance, and/or electric insulation.
FIG. 1B is a schematic view of a warpage phenomenon of a semiconductor substrate passing through a back-side polishing process.
Referring to FIG. 1B, a plurality of hetero-materials 20, 30, and 40 having different thermal expansion coefficients may be stacked on a semiconductor substrate 10a. A compressive stress may be generated about a central direction of the semiconductor substrate 10a. For example, the elastic protecting layer 40 may be formed as a thick layer compared to other stacked materials 20 and 30, and it may be a source of a compressive stress. The semiconductor substrate 10a may pass through the back-side polishing process. The semiconductor substrate 10a may be so thin that it may not have a sufficient stiffness to withstand the compressive stress. Thus, the semiconductor substrate 10a may be warped. The warpage may be from the bottom of the semiconductor substrate 10a toward the surface provided with the elastic protecting layer 40, and the corner of the semiconductor substrate 10a may be deformed to a height L.
A warped semiconductor substrate may induce performance defects in a semiconductor device. Further, the semiconductor substrate may be broken while being handled during a subsequent dicing process that may be used to form semiconductor chips. Packaging failure may also occur because sufficient contact area may not be available for the packaging die during the packaging process of the semiconductor chips.